1. Field of the Invention
The present invention relates to a liquid crystal display device. More particularly, the present invention relates to a liquid crystal display device and method of controlling the same, capable of preventing excitation voltage with respect to an option signal.
2. Description of the Related Art
Liquid crystal display devices (LCDs) are more widely used due to the characteristics of light weight, thin thickness, low-power-consumption driving, and so on. As a result, the LCDs are applied to office automation equipment, audio/video equipment, and so on. Meanwhile, the LCDs adjust an amount of transmitted light on the basis of image signals applied to a plurality of control switches arranged in a matrix pattern, thereby displaying a desired image on a screen.
The LCDs can change a data format, the driving mode of a timing controller, etc. through an option signal supplied from a system so as to be able to carry out a function selected by a user from the outside.
FIG. 1 is a view illustrating a related art LCD.
As illustrated in FIG. 1, the related art LCD includes a liquid crystal panel 2 having a plurality of gate lines GL1 through GLn and a plurality of data lines DL1 through DLm arranged, a gate driver 4 driving the plurality of gate lines GL1 through GLn, a data driver 6 driving the plurality of data lines DL1 through DLm, a timing controller 8 controlling the gate driver 4 and the data driver 6, and a user connector 10 supplying an option signal to the timing controller 8.
In the liquid crystal panel 2, the gate lines GL1 through GLn are arranged perpendicular to the data lines DL1 through DLm, and each intersection between the gate lines and the data lines has a thin film transistor (TFT) that is a switching element, and a pixel electrode that is electrically connected with the TFT.
The liquid crystal panel 2 includes a first substrate formed with the TFT and the pixel electrode, a second substrate formed with red, green, and blue color filters, and a liquid crystal layer formed between the first and second substrates.
The gate driver 4 sequentially supplies gate scan signals (gate high voltage and gate low voltage) to the gate lines GL1 through GLn on the basis of a gate control signal supplied from the timing controller 8.
The data driver 6 supplies data voltage to the data lines DL1 through DLm on the basis of a data control signal supplied from the timing controller 8.
The timing controller 8 generates the gate control signal controlling the gate driver 4 and the data control signal controlling the data driver 6 using vertical/horizontal synchronizing signals and a clock signal supplied from a system that is not shown.
When the option signal is supplied to the system so as to be able to perform a function that a user changes a data format or a driving mode of the timing controller from the outside, the system supplies the option signal to the user connector 10.
The user connector 10 supplies the option signal to an option pin of the timing controller 8 through a line. When the option signal is supplied to the option pin of the timing controller 8, the timing controller 8 performs the function corresponding to the option signal.
Specifically, the option signal is supplied to a node A to which first and second diodes D1 and D2 of the timing controller 8 are connected.
Meanwhile, the user connector 10 is connected with the option pin, i.e. the node A, of the timing controller 8 through the line. An excitation voltage such as static electricity (called ESD, electrostatic discharge) may be input into the line from the outside. When input into the line between the user connector 10 and the node A of the timing controller 8, this excitation voltage is supplied to the node A of the timing controller 8, so that the timing controller 8 causes malfunction.
More specifically, when supplied to the node A of the timing controller 8, the excitation voltage has an influence on a reset terminal of the timing controller 8, so that the timing controller 8 causes malfunction.
When the reset terminal is supplied with input voltage Vcc from the outside, the timing controller 8 is reset to prepare for driving. When the reset terminal carrying out this function is supplied with the excitation voltage having a level higher than that of the input voltage Vcc, the reset terminal may perform reset operation in spite of the circumstance that the reset terminal should not perform the reset operation. For this reason, the timing controller 8 causes malfunction.
As described above, when the excitation voltage is input into the reset terminal of the timing controller 8, the timing controller 8 has a problem in that it causes malfunction.